1. Field of the Invention
The present invention relates to a semiconductor memory device and an information processor using the semiconductor memory device, and more particularly to a semiconductor memory device and an information processor using the semiconductor memory device capable of executing pipeline processing for data reading and writing.
2. Description of the Related Art
In a conventional processor, in order to increase memory access speed, a second cache is often provided using synchronous SRAMs for data and for tag outside a processor chip in addition to an on-chip cache memory. The synchronous SRAM is a SRAM incorporating a register to carry out pipeline processing. Conventional synchronous SRAMs are described, for example, in Hitachi IC Memory Data Book, pp 899-909, edited by Hitachi Micro-computer System Technology Document Center, published by Semiconductor Department of Hitachi Ltd. FIG. 36 to FIG. 39 are drawings explaining the above examples. FIG. 36 is a view showing the arrangement of pins in a synchronous SRAM. FIG. 37 is a table explaining the functions of the pins. FIG. 38 is an overall block diagram of the synchronous SRAM. FIG. 39 is a chart explaining the operation timings of the synchronous SRAM under writing process. As shown in FIG. 36 and FIG. 37, the signal instructing to write data to a memory from a processor is only a WE (Write Enable) signal. The synchronous SRAM shown in FIG. 38 has registers in an address part and a data part. As shown in FIG. 39, at executing writing in the synchronous SRAM, address and data are delivered at the same time and further the WE signal is turned to low-state at the same timing.
Generally, as to control methods for a second cache, there is a write-through method where data is written both in a second cache and in a main memory, and a store-in method where data is written only in a second cache and the line in the second cache is rewritten in a main memory a line unit just before the line is to be overwritten by a new line.
In the store-in method, there is a dirty bit expressing that the line has been written. Although the store-in method is complex in control, it is known that the performance is generally improved since frequency of writing to the main memory is reduced. These technologies are described in the article by John Hennessy and David Patterson, "Quantitative Approach to Computer Architecture", pp 412-414, Morgan Knafmann Publishers, Inc.
Two processes of reading and writing are executed to the second cache. In the read process, reading is executed for a RAM for data and a RAM for tag at a time. However, in write process, data cannot be written in the RAM for data until a tag is read to execute a hit judgement. Therefore, since the timing of data transfer in the conventional method is different depending on whether a reading process or a writing process, it has been difficult to improve the throughput by pipelining by 1 cycle pitch. Further, the machine cycle is decreased due a bottle neck effect that occurs during a writing process, and the throughput is decreased as the result.